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direct rdram ? page -1 k4r761869a version 1.41 jan. 2004 january 2004 version 1.41 direct rdram tm 1m x 18bit x 32s banks 576mbit rdram ? (a-die)
direct rdram ? page 0 k4r761869a version 1.41 jan. 2004 change history version 1.4( sept. 2003) - first copy ( version 1.4 is named to unify the version of component and device operation datasheets) - based on the 256/288mb d-die version 1.4 version 1.41(jan. 2004) - add the part numbers for lead free package - correct the package total thickness
direct rdram ? page 1 k4r761869a version 1.41 jan. 2004 overview the rdram ? device is a gene ral purpose high-perfor- mance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. the 576mbit rdram devices are extremely high-speed cmos drams organized as 32m words by 18 bits. the use of rambus signaling level (rsl) technology permits up to 1200 mhz transfer rates while using conventional system and board design technologies. rdram devices are capable of sustained data transfers up to 0.833ns per two bytes (6.7ns per sixteen bytes). the architecture of rdram devices allows the highest sustained bandwidth for multi ple, simultaneous randomly addressed memory transactions . the separate control and data buses with independent row and column control yield over 95% bus efficiency. th e rdram device's 32 banks support up to four simult aneous transactions. system oriented features fo r mobile, graphics and large memory systems include power management, byte masking, and x18 organization. the two da ta bits in the x18 organiza- tion are general and can be us ed for additional storage and bandwidth or for error correction. features ? highest sustained bandw idth per dram device - 2.4gb/s sustained data transfer rate - separate control and data buses for maximized efficiency - separate row and column control buses for easy scheduling and highest performance - 32 banks: four transacti ons can take place simul- taneously at full bandwidth data rates ? low latency features - write buffer to reduce read latency - 3 precharge mechanisms for controller flexibility - interleaved transactions ? advanced power management: - multiple low power states allows flexibility in power consumption versus time to transition to active state - power-down self-refresh ? organization: 2kbyte pages and 32 banks, x18 - x18 organization allows ecc configurations or increased storage/bandwidth ? uses rambus signa ling level (rsl) for up to 1200mhz operation the 576mbit rdram devices are offered in a csp hori- zontal package suitable for de sktop as well as low-profile add-in card and m obile applications. key timing parameters/part numbers figure 1: direct rdram csp package organization speed part number bin i/o freq. mhz t rac (row access time) ns 1mx18x32s a a. ? 32s ? - 32 banks which use a ? split ? bank architecture . -cn1 1200 32 k4r761869a-f b c c n1 b. ? f ? - wbga package, ?g?- wbga lead free package. c. ? c ? - rdram core uses normal power self refresh. -ct9 1066 32p k4r761869a-fct9 -cm8 800 40 k4r761869a-fcm8 1mx18x32s -cn1 1200 32 k4r761869a-gcn1 -ct9 1066 32p k4r761869a-gct9 -cm8 800 40 k4r761869a-gcm8 k4r761869a- x cxx samsung 320 k4r761869a- cxx samsung 320 k4r761869a- cxx samsung 320 k4r761869a- x cxx samsung 320 k4r761869a- cxx samsung 320 k4r761869a- cxx samsung 320
direct rdram ? page 2 version 1.41 jan. 2004 k4r761869a col row pinouts and definitions center-bonded devices these tables shows the pin a ssignments of the center-bonded rdram package. the mechanical dimensions of this package are shown in a later section. refer to section ? center-bonded wbga package ? on page 18. note - pin #1 is at the a1 position. table 1: center-bonded device (top view) 10 v dd gnd v dd gnd v dd v dd v dd v dd gnd v dd 9 8 gnd v dd cmd v dd gnd gnda gnda v dd v dd gnd gnd v dd v dd gnd gnd v cmos v dd gnd 7 v dd dqa8 dqa7 dqa5 dqa3 dqa1 ctmn ctm rq7 rq5 rq3 rq1 dqb1 dqb3 dqb5 dqb7 dqb8 v dd 6 5 4 gnd gnd dqa6 dqa4 dqa2 dqa0 cfm cfmn rq6 rq4 rq2 rq0 dqb0 dqb2 dqb4 dqb6 gnd gnd 3 v dd gnd sck v cmos gnd v dd gnd v dda v ref gnd v dd gnd gnd v dd sio0 sio1 gnd v dd 2 1 v dd gnd gnd v dd gnd gnd gnd gnd gnd v dd a b c d e f g h j k l m n p r s t u chip top view the pin #1(row 1, col a) is located at the a1 position on the top side and the a1 position is marked by the marker ? ? . k4r761869a- x cxx samsung 320 k4r761869a- x cxx samsung 320
direct rdram ? page 3 k4r761869a version 1.41 jan. 2004 table 2: pin description signal i/o type # pins center description sio1,sio0 i/o cmos a 2 serial input/output. pins for reading from and writing to the control regis- ters using a serial access protoc ol. also used for power management. cmd i cmos a 1 command input. pins used in conjuncti on with sio0 and sio1 for reading from and writing to the control r egisters. also used for power manage- ment. sck i cmos a 1 serial clock input. clock source us ed for reading from and writing to the control registers v dd 24 supply voltage for the rdram core and interface logic. v dda 1 supply voltage for the rdram analog circuitry. v cmos 2 supply voltage for cmos input/output pins. gnd 28 ground reference for rdram core and interface. gnda 2 ground reference for rdram analog circuitry. dqa8..dqa0 i/o rsl b 9 data byte a. nine pins which carry a byte of read or write data between the channel and the rdram device. dq a8 is not used (no connection) by rdram device with a x16 organization. cfm i rsl b 1 clock from master. interface clock used for receiving rsl signals from the channel. positive polarity. cfmn i rsl b 1 clock from master. interface clock used for receiving rsl signals from the channel. negative polarity v ref 1 logic threshold reference voltage for rsl signals ctmn i rsl b 1 clock to master. interface clock used for transmitting rsl signals to the channel. negative polarity. ctm i rsl b 1 clock to master. interface clock used for transmitting rsl signals to the channel. positive polarity. rq7..rq5 or row2..row0 irsl b 3 row access control. three pins c ontaining control and address informa- tion for row accesses. rq4..rq0 or col4..col0 irsl b 5 column access control. five pins containing control and address informa- tion for column accesses. dqb8.. dqb0 i/o rsl b 9 data byte b. nine pins which carry a byte of read or write data between the channel and the rdram device. dq b8 is not used (no connection) by rdram device with a x16 organization. total pin count per package 92 a. all cmos signals are high-true; a high voltage is a logic one and a low voltage is logic zero. b. all rsl signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
direct rdram ? page 4 version 1.41 jan. 2004 k4r761869a figure 2: 576mbit (1m x18 x32s) rdram device block diagram bank 31 dqa8..dqa0 1:8 demux 8:1 mux write buffer 1:8 demux write buffer 8:1 mux bank 30 bank 29 bank 18 bank 17 bank 16 bank 15 bank 14 bank 13 bank 1 bank 0 samp 1/2 dqb8..dqb0 9 1:8 demux 1:8 demux packet decode 9 5 3 row2..row0 col4..col0 ctm ctmn cfm cfmn 2 sck,cmd rclk tclk control registers dc cop c bc ma mb dx xop bx dr r rop br 8 8 7 5 5 5 5 5 6 10 5 5 11 av m s write buffer match match mux match devid 1024x128x144 internal dqb data path column decode & mask 72 9 9 72 9 dm refr row decode mux act rd, wr power modes dram core mux xop decode prex prec 9 9 9 9 72 9 9 9 prer colx colc colm 2 sio0,sio1 sense amp internal dqa data path packet decode rowa rowr rclk rclk rclk tclk rclk tclk r q 7..r q 5 or rq4..rq0 or samp 0/1 samp 0 samp 14/15 samp 15 samp 13/14 samp 16/17 samp 17/18 samp 16 samp 29/30 samp 30/31 samp 31 64x72 samp 1/2 72 samp 0/1 samp 0 samp 14/15 samp 15 samp 13/14 samp 16/17 samp 17/18 samp 16 samp 29/30 samp 30/31 samp 31 64x72 64x72 bank 2 ??? ??? ??? ??? ??? ???
direct rdram ? page 5 k4r761869a version 1.41 jan. 2004 general description figure 2 is a block diagram of the 576mbit rdram device. it consists of two major blocks: a ? core ? block built from banks and sense amps similar to those found in other types of dram, and a direct rambus tm interface block which permits an external controller to access this core at up to 2.4gb/s. control registers: the cmd, sck, sio0 and sio1 pins appear in the upper center of figure 2. they are used to write and read a block of cont rol registers. these registers supply the rdram configuration information to a controller and they select th e operating modes of the device. the refr value is used for tracking the last refreshed row. most importantly, the five bit devid specifies the device address of the rdram device on the channel. clocking: the ctm and ctmn pi ns (clock-to-master) generate tclk (transmit clock), the internal clock used to transmit read data. the cfm and cfmn pins (clock-from- master) generate rcl k (receive clock), the internal clock signal used to receive write da ta and to receive the row and col pins. dqa,dqb pins: these 18 pins carry read (q) and write (d) data across the channel. they are multiplexed/de-multi- plexed from/to two 72-bit data paths (running at one-eighth the data frequency) insi de the rdram device. banks: the 64mbyte core of the rdram device is divided into thirty two 2mbyt e banks, each organized as 1024 rows, with each row cont aining 128 dualocts, and each dualoct containing 18 bytes. a dualo ct is the smallest unit of data that can be addressed. sense amps: the rdram device contains 34 sense amps. each sense amp consists of 1kbyte of fast storage (512 bytes for dqa and 512 bytes for dqb) and can hold one- half of one row of one ba nk of the rdram device. the sense amp may hold any of the 1024 half-rows of an associ- ated bank. however, each sens e amp is shared between two adjacent banks of the rdra m device (except for sense amps 0, 15, 16, and 31). this introduces the restriction that adjacent banks may not be simultaneously accessed. rq pins: these pins carry cont rol and address informa- tion. they are broken into two groups. rq7..rq5 are also called row2..row0, and are us ed primarily for controlling row accesses. rq4..rq0 are also called col4..col0, and are used primarily for controlling column accesses. row pins: the principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the rdram device. th ese pins are de-multiplexed into a 24-bit rowa (row-activate) or rowr (row-opera- tion) packet. col pins: the principle use of th ese five pins is to manage the transfer of data between the dqa/dqb pins and the sense amps of the rdram device. these pins are de- multiplexed into a 23-bit colc (column-operation) packet and either a 17-bit colm (mas k) packet or a 17-bit colx (extended-opera tion) packet. act command: an act (activate) command from an rowa packet causes one of the 1024 rows of the selected bank to be loaded to its as sociated sense amps (two 512 bytes sense amps for dqa and two for dqb). prer command: a prer (precharge) command from an rowr packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permi tting adjacent banks to be acti- vated. rd command: the rd (read) command causes one of the 128 dualocts of one of the se nse amps to be transmitted on the dqa/dqb pins of the channel. wr command: the wr (write) command causes a dualoct received from the dqa/dqb data pins of the channel to be loaded into the write buffer. there is also space in the write buffer for the bc bank address and c column address information. the data in the write buffer is automatically retired (written with optional bytemask) to one of the 128 dualocts of one of the sense amps during a subse- quent cop command. a retire can take place during a rd, wr, or nocop to another device, or during a wr or nocop to the same device. the write buffer will not retire during a rd to the same device . the write buffer reduces the delay needed for the internal dqa/dqb data path turn- around. prec precharge: the prec, rda and wra commands are similar to nocop, rd and wr, except that a precharge operation is performed at the end of the column operation. these commands provide a second mechanism for performing precharge. prex precharge: after a rd command, or after a wr command with no byte masking (m =0), a colx packet may be used to specify an exte nded operation (xop). the most important xop command is prex. this command provides a third mechanism for performing precharge.
direct rdram ? page 6 version 1.41 jan. 2004 k4r761869a packet format figure 3 shows the formats of the rowa and rowr packets on the row pins. table 3 describes the fields which comprise these packets. dr4t and dr4f bits are encoded to contain both the dr4 device address bit and a framing bit which allows the rowa or ro wr packet to be recognized by the rdram device. the av (rowa/rowr packet se lection) bit distinguishes between the two packet types. both the rowa and rowr packet provide a five bit devi ce address and a five bit bank address. an rowa packet uses the remaining bits to specify a nine bit row address, and the rowr packet uses the remaining bits for an eleven b it opcode field. note the use of the ? rsvx ? notation to reserve bits for future address field extension. figure 3 also shows the formats of the colc, colm, and colx packets on the col pins. table 4 describes the fields which comprise these packets. the colc packet uses the s (start) bit for framing. a colm or colx packet is ali gned with this colc packet, and is also framed by the s bit. the 23 bit colc packet has a five bit device address, a five bit bank address, a seven bit co lumn address, and a four bit opcode. the colc packet sp ecifies a read or write command, as well as some power management commands. the remaining 17 bits are inte rpreted as a colm (m=1) or colx (m=0) packet. a colm pa cket is used for a colc write command which needs byt emask control. the colm packet is associated with the colc packet from at least t rtr earlier. a colx packet may be used to specify an indepen- dent precharge command. it contains a five bit device address, a five bit bank addre ss, and a five bit opcode. the colx packet may also be used to specify some house- keeping and power manageme nt commands. the colx packet is framed within a colc packet but is not otherwise associated with any other packet. table 3: field description for rowa packet and rowr packet field description dr4t,dr4f bits for framing (recognizing) a rowa or rowr packet. also encodes highest device address bit. dr3..dr0 device address for rowa or rowr packet. br4..br0 bank address for rowa or rowr p acket. rsvb denotes bi ts ignored by the rdram device . av selects between rowa packet (a v=1) and rowr packet (av=0). r9..r0 row address for rowa packet. rsvr denotes bits ignored by the rdram device . rop10..rop0 opcode field for rowr packet. specifies precharge, refresh, and power management functions. table 4: field description for colc packet, colm packet, and colx packet field description s bit for framing (recognizing) a colc packet, and indirectly for framing colm and colx packets. dc4..dc0 device addres s for colc packet. bc4..bc0 bank address for colc packet. rs vb denotes bits reserved for future extension (controller drives 0 ? s). c6..c0 column address for colc packet. rsvc denotes bits ignored by the rdram device 02. cop3..cop0 opcode field for colc packet. specifi es read, write, precharge, and power management functions. m selects between colm packet (m=1) and colx packet (m=0). ma7..ma0 bytemask write control bits. 1=write, 0=no-write. ma0 controls the earliest byte on dqa8..0. mb7..mb0 bytemask write control bits. 1=write, 0=no-write. mb0 controls the earliest byte on dqb8..0. dx4..dx0 device addres s for colx packet. bx4..bx0 bank address for colx packet. rsvb denotes bits reserved for future extension (c ontroller drives 0? s). xop4..xop0 opcode fiel d for colx packet. specifies precharge, i ol control, and power management functions.
direct rdram ? page 7 k4r761869a version 1.41 jan. 2004 figure 3: packet formats ctm/cfm col4 col3 col2 col1 col0 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 8 t 9 t 10 t 11 t 0 t 1 t 2 t 3 t 0 t 1 t 2 t 3 s=1 a ma7 ma5 ma3 ma1 m=1 ma6 ma4 ma2 ma0 mb7 mb4 mb1 mb6 mb3 mb0 mb5 mb2 r2 ctm/cfm row2 dr4t dr2 br0 br3 rsvr r8 r5 row1 dr4f dr1 br1 br4 r9 r7 r4 r1 row0 dr3 dr0 br2 rsvb av = 1 r6 r3 r0 act a0 prex d0 msk (b1) prer c0 wr b1 c4 ctm/cfm col4 dc4 s=1 c6 col3 dc3 c5 c3 col2 dc2 cop1 rsvb bc2 c2 dc1 cop0 bc4 bc1 c1 dc0 cop2 cop3 bc3 bc0 c0 col1 col0 ctm/cfm row2 row1 row0 ctm/cfm col4 col3 col2 col1 col0 rop2 dr4t dr2 br0 br3 rop10 rop8 rop5 dr4f dr1 br1 br4 rop9 rop7 rop4 rop1 dr3 dr0 br2 rsvb av = 0 rop6 rop3 rop0 s=1 b dx4 xop4 rsvb bx1 m=0 dx3 xop3 bx4 bx0 dx2 xop2 bx3 dx1 xop1 bx2 dx0 xop0 t 0 t 4 t 8 t 12 t 1 t 5 t 9 t 13 t 2 t 6 t 10 t 14 t 3 t 7 t 11 t 15 rowa packet colm packet colc packet colx packet rowr packet ctm/cfm dqa8..0 dqb8..0 col4 ..col0 row2 ..row0 t packet a the colm is associated with a previous colc, and is aligned with the present colc, indicated by the start bit (s=1) position. b the colx is aligned with the present colc, indicated by the start bit (s=1) position.
direct rdram ? page 8 version 1.41 jan. 2004 k4r761869a field encoding summary table 5 shows how the six devi ce address bits are decoded for the rowa and rowr packets. the dr4t and dr4f encoding merges a fifth device bit with a framing bit. when neither bit is a sserted, the device is not selected. note that a broadcast operation is indicated when both bits are set. broadcast operation w ould typically be us ed for refresh and power management commands. if the device is selected, the dm (devicematch) signal is asserted and an act or rop command is performed. table 6 shows the encodings of the remaining fields of the rowa and rowr packets. an rowa packet is specified by asserting the av bit. this ca uses the specified row of the specified bank of this device to be loaded into the associated sense amps. an rowr packet is specified when av is not asserted. an 11 bit opcode field encodes a command for one of the banks of this device. the prer co mmand causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activa ted. the refa (refresh-acti- vate) command is similar to the act command, except the row address comes from an internal register refr, and refr is incremented at the largest bank address. the refp (refresh-precharge) command is identical to a prer command. the napr, naprc, pdnr, attn, and rlxr commands are used for managing the power dissipation of the rdram device and are descri bed in more detail in ? power state management ? on page 50. the tcen and tcal commands are used to adjust the output dr iver slew rate and they are described in more detail in ? current and temperature control ? on page 56. table 5: device field encodings for rowa packet and rowr packet dr4t dr4f device selection d evice match signal (dm) 1 1 all devices (broadcast) dm is set to 1 0 1 one device selected dm is set to 1 if {devid4..devid0} == {0,dr3..dr0} else dm is set to 0 1 0 one device selected dm is set to 1 if {devid4..devid0} == {1,dr3..dr0} else dm is set to 0 0 0 no packet present dm is set to 0 table 6: rowa packet and rowr packet field encodings dm a av rop10..rop0 field name command description 1098765432:0 0 - ------------ no operation. 1 1 row address act activate row r9..r0 of bank br4..br0 of device and move device to attn b . 10 1 1000x c x x 000 prer precharge bank br4..br0 of this device. 10000 1 100x000refa refresh (activate) row refr9..refr0 of bank br4..br0 of device. increment refr if br4..br0 = 11111 (see figure 52). 10 10 10 1 0 0 x 000 refp precharge bank br4..br0 of this device after refa (see figure 52). 1 0 xx000 0 1 x 000 pdnr move this device into the powerdown (pdn) power state (see figure 49). 1 0 xx000 1 0 x 000 napr move this device into the nap (nap) power state (see figure 49). 1 0 xx000 1 1 x 000 naprc move this device into the nap (nap) power state conditionally 1 0 xxxxxxx 0 000 attn b move this device into the attention (attn) power state (see figure 47). 1 0 xxxxxxx 1 000 rlxr move this device into the standby (stby) power state (see figure 48). 1 0 0000000x 001 tcal temperature calibrate this device (see figure 55). 1 0 0000000x 010 tcen temperature calibrate/enable this device (see figure 55). 1 0 00000000000noropno operation. a. the dm (device match signal) value is determined by the dr4t,dr4f, dr3..dr0 field of the rowa and rowr packets. see table 5. b. the attn command does not cause a rlx-to-attn transition for a broadcast operation (dr4t/dr4f=1/1). c. an ? x ? entry indicates which commands may be combined. for instance, the three commands prer/naprc/rlxr may be specified in one rop v alue (011000111000).
direct rdram ? page 9 k4r761869a version 1.41 jan. 2004 table 7 shows the cop field en coding. the device must be in the attn power state in order to receive colc packets. the colc packet is used prima rily to specify rd (read) and wr (write) commands. retire operations (moving data from the write buffer to a sense amp) happen automatically. see figure 18 for a more detailed description. the colc packet can also specify a prec command, which precharges a bank and it s associated sense amps. the rda/wra commands are equiva lent to combining rd/wr with a prec. rlxc (relax) performs a power mode transi- tion. see ? power state management ? on page 50. table 8 shows the colm and colx field encodings. the m bit is asserted to specify a colm packet with two 8 bit bytemask fields ma and mb. if th e m bit is not asserted, an colx is specified. it has de vice and bank a ddress fields, and an opcode field. the primary use of the colx packet is to permit an independent prex (precharge) command to be specified without consuming control bandwidth on the row pins. it is also used for th e cal(calibrate) and sam (sam- ple) current control commands (see ? current and tempera- ture control ? on page 56), and for the rlxx power mode command (see ? power state management ? on page 50). table 7: colc packet field encodings s dc4.. dc0 (select device) a cop3..0 name command description 0 ---- ----- - no operation. 1 /= (devid4 ..0) ----- - retire write buffer of this device. 1 == (devid4 ..0) x000 b nocop retire write buffer of this device. 1 == (devid4 ..0) x001 wr retire write buffer of this device, then write column c6..c0 of bank bc4..bc0 to write buffer. 1 == (devid4 ..0) x010 rsrv reserved, no operation. 1 == (devid4 ..0) x011 rd read column c6..c0 of bank bc4..bc0 of this device. 1 == (devid4 ..0) x100 prec retire write buffer of this device, then precharge bank bc4..bc0 (see figure 15). 1 == (devid4 ..0) x101 wra same as wr, but precharge bank bc4..bc0 after write buffer (with new data) is retired. 1 == (devid4 ..0) x110 rsrv reserved, no operation. 1 == (devid4 ..0) x111 rda same as rd, but precharge bank bc4..bc0 afterward. 1 == (devid4 ..0) 1xxx rlxc move this device into the standby (stby) power state (see figure 48). a. ? /= ? means not equal, ? == ? means equal. b. an ? x ? entry indicates which commands may be combined. for instance, the two commands wr/rlxc may be specified in one cop value (1001 ). table 8: colm packet and colx packet field encodings m dx4 .. dx0 (selects device) xop4..0 name command description 1 ---- - msk mb/ma bytemasks used by wr/wra. 0 /= (devid4 ..0) - - no operation. 0 == (devid4 ..0) 00000 noxop no operation. 0 == (devid4 ..0) 1xxx0 a prex precharge bank bx3..bx0 of this device (see figure 15). 0 == (devid4 ..0) x10x0 cal calibrate (drive) i ol current for this device (see figure 54). 0 == (devid4 ..0) x11x0 cal/sam calibrate (drive) and sample ( update) i ol current for this device (see figure 54). 0 == (devid4 ..0) xxx10 rlxx move this device into the standby (stby) power state (see figure 48). 0 == (devid4 ..0) xxxx1 rsrv reserved, no operation. a. an ? x ? entry indicates which commands may be combined. for instance, the two commands prex/rlxx may be specified in one xop value (10 010).
direct rdram ? page 10 version 1.41 jan. 2004 k4r761869a electrical conditions table 9: electrical conditions symbol parameter and conditions min max unit t j junction temperature under bias - 100 c v dd, v dda supply voltage 2.50 - 0.13 2.50 + 0.13 v v dd,n, v dda,n supply voltage droop (dc) during nap interval (t nlimit ) - 2.0 % v dd,n, v dda,n supply voltage ripple (ac) during nap interval (t nlimit ) -2.0 2.0 % v cmos a supply voltage for cmos pins (2.5v controllers) supply voltage for cmos pins (1.8v controllers) v dd 1.80 - 0.1 v dd 1.80 + 0.2 v v v ref reference voltage 1.40 - 0.2 1.40 + 0.2 v v dil rsl data input - low voltage @ t cycle =1.667ns v ref - 0.5 v ref - 0.15 v rsl data input - low voltage @ t cycle =1.875ns v ref - 0.5 v ref - 0.15 rsl data input - low voltage @ t cycle =2.50ns v ref - 0.5 v ref - 0.2 v dih rsl data input - high voltage b @ t cycle =1.667ns v ref + 0.15 v ref + 0.5 rsl data input - high voltage b @ t cycle =1.875ns v ref + 0.15 v ref + 0.5 v rsl data input - high voltage b @ t cycle =2.50ns v ref + 0.2 v ref + 0.5 r da rsl data asymmetry : r da = (v dih - v ref ) / (v ref - v dil ) 0.67 1.00 - v cm rsl clock input - common mode v cm = (v cih +v cil) /2 1.3 1.8 v v cis,ctm rsl clock input swing: v cis = v cih - v cil (ctm,ctmn pins). 0.35 1.00 v v cis,cfm rsl clock input swing: v cis = v cih - v cil (cfm,cfmn pins). 0.225 1.00 v v il,cmos cmos input low voltage - 0.3 c v cmos /2 - 0.25 v v ih,cmos cmos input high voltage v cmos /2 + 0.25 v cmos +0.3 d v a. v cmos must remain on as long as v dd is applied and cannot be turned off. b. v dih is typically equal to v term (1.8v 0.1v) under dc conditions in a system. c. voltage undershoot is limited to -0.7v for a duration of less than 5ns. d. voltage overshoot is limited tov cmos +0.7v for a duration of less than 5ns
direct rdram ? page 11 k4r761869a version 1.41 jan. 2004 electrical characteristics table 10: electric al characteristics symbol parameter and conditions min max unit jc junction-to-case thermal resistance - 0.5 c/watt i ref v ref current @ v ref,max -10 10 a i oh rsl output high current @ (0 v out v dd ) -10 10 a i all rsl i ol current @ t cycle = 1.667ns v ol = 0.9v, v dd,min , t j,max a a. this measurement is made in manual current contro l mode; i.e. with all output device legs sinking current. 32.0 90.0 ma rsl i ol current @ t cycle = 1.875ns v ol = 0.9v, v dd,min , t j,max a 32.0 90.0 rsl i ol current @ t cycle =2.50ns v ol = 0.9v, v dd,min , t j,max a 30.0 90.0 ? i ol rsl i ol current resolution step - 1.5 ma r out dynamic output impedance @ v ol = 0.9v 150 - ? i ol,nom rsl i ol current @ v ol = 1.0v b,c @ t cycle =1.667ns b. this measurement is made in automatic current control mode after at least 64 current control calibration operations to a dev ice and after cca and ccb are initialized to a value of 64. this value applies to all dqa and dqb pins. c. this measurement is made in automatic current control mode in a 25 ? test system with v term = 1.714v and v ref = 1.357v and with the asyma and asymb register fields set to 0. 27.1 30.1 ma rsl i ol current @ v ol = 1.0v b,c @ t cycle =1.875ns 27.1 30.1 rsl i ol current @ v ol = 1.0v b,c @ t cycle =2.5ns 26.6 30.6 i i,cmos cmos input leakage current @ (0 v i,cmos v cmos ) -10.0 10.0 a v ol,cmos cmos output voltage @ i ol,cmos = 1.0ma - 0.3 v v oh,cmos cmos output high voltage @ i oh,cmos = -0.25ma v cmos -0.3 - v
direct rdram ? page 12 version 1.41 jan. 2004 k4r761869a timing conditions table 11: timing conditions symbol parameter min max unit figure(s) t cycle ctm and cfm cycle times (-1200) 1.667 2.5 ns figure 56 ctm and cfm cycle times (-1066) 1.875 2.5 ctm and cfm cycle times (-800) 2.50 3.33 t cr , t cf ctm and cfm input rise and fall times. use the minimum value of these parameters during testing. (-1200) 0.2 0.45 ns figure 56 ctm and cfm input rise and fall times. use the minimum value of these parameters during testing. (-1066,-800) 0.2 0.5 t ch , t cl ctm and cfm high and low times 40% 60% t cycle figure 56 t tr ctm-cfm differential (mse/ms=0/0) ctm-cfm differential (mse/ms=1/1) a ctm-cfm differential only for 1.875ns and 1.667ns (mse/ms=1/0) 0.0 0.9 -0.1 1.0 1.0 0.1 t cycle figure 43 figure 56 t dcw domain crossing window -0.1 0.1 t cycle figure 62 t dr , t df dqa/dqb/row/col input rise/fall times (20% to 80%). use the minimum value of these parameters during testing.@ t cycle =1.667ns 0.2 0.45 ns figure 57 dqa/dqb/row/col input rise/fall times (20% to 80%). use the minimum value of these parameters during testing.@ t cycle =1.875ns 0.2 0.45 dqa/dqb/row/col input rise/fall times (20% to 80%). use the minimum value of these parameters during testing.@ t cycle =2.50ns 0.2 0.65 t s , t h dqa/dqb/row/col-to-cfm set/hold @ t cycle =1.667ns 0.140 b - ns figure 57 dqa/dqb/row/col-to-cfm set/hold @ t cycle =1.875ns 0.160 b,c - dqa/dqb/row/col-to-cfm set/hold @ t cycle =2.50ns 0.200 b.d - t dr1, t df1 sio0, sio1 input rise and fall times - 5.0 ns figure 59 t dr2, t df2 cmd, sck input rise and fall times - 2.0 ns figure 59 t cycle1 sck cycle time - serial control register transactions 1000 - ns figure 59 sck cycle time - power transitions @ t cycle =1.667ns 7.5 - sck cycle time - power transitions @ t cycle =1.875ns 7.5 - sck cycle time - power transitions @ t cycle =2.50ns 10 - t ch1 , t cl1 sck high and low times @ t cycle =1.667ns 3.5 - ns figure 59 sck high and low times @ t cycle =1.875ns 3.5 - sck high and low times @ t cycle =2.50ns 4.25 - t s1 cmd setup time to sck rising or falling edge e @ t cycle =1.667ns 1.0 - ns figure 59 cmd setup time to sck rising or falling edge e @ t cycle =1.875ns 1.0 - cmd setup time to sck rising or falling edge e @ t cycle =2.50ns 1.25 - t h1 cmd hold time to sck rising or falling edge e 1 - ns figure 59
direct rdram ? page 13 k4r761869a version 1.41 jan. 2004 t s2 sio0 setup time to sck falling edge 40 - ns figure 59 t h2 sio0 hold time to sck falling edge 40 - ns figure 59 t s3 pdev setup time on dqa5..0 to sck rising edge. 0 - ns figure 50 t h3 pdev hold time on dqa5..0 to sck rising edge. 5.5 - ns figure 60 t s4 row2..0, col4..0 setup time for quiet window -1 - t cycle figure 50 t h4 row2..0, col4..0 hold time for quiet window f 5-t cycle figure 50 t npq quiet on row/col bits during nap/pdn entry 4 - t cycle figure 49 t readtocc offset between read data and cc packets (same device) 12 - t cycle figure 54 t ccsamtoread offset between cc packet and read data (same device) 8 - t cycle figure 54 t ce ctm/cfm stable before nap/pdn exit 2 - t cycle figure 50 t cd ctm/cfm stable after nap/pdn entry 100 - t cycle figure 49 t frm row packet to col packet attn framing delay 7 - t cycle figure 48 t nlimit maximum time in nap mode 10.0 ms figure 47 t ref refresh interval 32 ms figure 52 t burst interval after pdn or nap (with self-refresh) exit in which all banks of the rdram device must be refreshed at least once. 200 ms figure 53 t cctrl current control interval 34 t cycle 100ms ms/t cycle figure 54 t temp temperature control interval 100 ms figure 55 t tcen tce command to tcal command 150 - t cycle figure 55 t tcal tcal command to quiet window 2 2 t cycle figure 55 t tcquiet quiet window (no read data) 140 - t cycle figure 55 t pa use rdram device delay (no rsl operations allowed) 200.0 ms page 38 a. mse/ms are fields of the skip register. for this combinati on (skip override) the tdcw parameter range is effectively 0.0 to 0.0. b. t s,min and t h,min for other t cycle values can be interpolated between or extr apolated from the timings at the 2 specified t cycle values. c. this parameter also applies to a-1200 part when operated with t cycle = 1.875ns d. this parameter also applies to a-1200 or -1066 part when operated with t cycle = 2.50ns e. with v il,cmos =0.5v cmos -0.4v and v ih,cmos =0.5v cmos +0.4v f. effective hold becomes t h4 ?=t h4 +[pdnxa?64?t scycle +t pdnxb,max ]-[pdnx?256?t scycle ] if [pdnx?256?t scycle ] < [pdnxa?64?t scycle +t pd- nxb,max ]. see figure 50 table 11: timing conditions symbol parameter min max unit figure(s)
direct rdram ? page 14 k4r761869a version 1.41 jan. 2004 timing characteristics table 12: timing characteristics symbol parameter min max unit figure(s) t q ctm-to-dqa/dqb output time @ t cycle =1.667ns -0.170 a a. t q,min and t q,max for other t cycle values can be interpolated between or extrapolated from the timings at the 3 specified t cycle values. b. this parameter also applies to a-1200 part when operated with t cycle = 1.875ns c. this parameter also applies to a-1200 or -1066 part when operated with t cycle = 2.50ns +0.170 a ns figure 58 ctm-to-dqa/dqb output time @ t cycle =1.875ns -0.195 a,b +0.195 a,b ctm-to-dqa/dqb output time @ t cycle =2.5ns -0.260 a,c +0.260 a,c t qr , t qf dqa/dqb output rise and fall times @ t cycle =1.667ns 0.2 0.32 ns figure 58 dqa/dqb output rise and fall times @ t cycle =1.875ns 0.2 0.32 dqa/dqb output rise and fall times @ t cycle =2.5ns 0.2 0.45 t q1 sck(neg)-to-sio0 delay @ c load,max = 20pf (sd read data valid). - 10 ns figure 61 t hr sck(pos)-to-sio0 delay @ c load,max = 20pf (sd read data hold). 2 - ns figure 61 t qr1 , t qf1 sio out rise/fall @ c load,max = 20pf - 12 ns figure 61 t prop1 sio0-to-sio1 or sio1-to-sio0 delay @ c load,max = 20pf - 20 ns figure 61 t napxa nap exit delay - phase a - 50 ns figure 50 t napxb nap exit delay - phase b - 40 ns figure 50 t pdnxa pdn exit delay - phase a - 4 s figure 50 t pdnxb pdn exit delay - phase b - 9000 t cycle figure 50 t as attn-to-stby power state delay - 1 t cycle figure 48 t sa stby-to-attn power state delay - 0 t cycle figure 48 t asn attn/stby-to-nap power state delay - 8 t cycle figure 49 t asp attn/stby-to-pdn power state delay - 8 t cycle figure 49
direct rdram ? page 15 k4r761869a version 1.41 jan. 2004 timing parameters table 13: timing parameter summary parameter description min -32 -1200 min -32p -1066 min -40 -800 max units figure(s) t rc row cycle time of rdram banks -the interval between rowa packets with act commands to the same bank. 32 28 28 - t cycle figure 16 figure 17 t ras ras-asserted time of rdram bank - the interval between rowa packet with act command and next rowr packet with prer a command to the same bank. 22 20 20 64 s b t cycle figure 16 figure 17 t rp row precharge time of rdram banks - the interval between rowr packet with prer a command and next rowa packet with act command to the same bank. 10 8 8 - t cycle figure 16 figure 17 t pp precharge-to-precharge time of rdram device - the interval between successive rowr packets with prer a commands to any banks of the same device. 888-t cycle figure 13 t rr ras-to-ras time of rdram device - the interval between succes- sive rowa packets with act commands to any banks of the same device. 888-t cycle figure 14 t rcd ras-to-cas delay - the interval from rowa packet with act command to colc packet with rd or wr command). note - the ras-to-cas delay seen by the rdram core (t rcd-c ) is equal to t rcd-c = 1 + t rcd because of differences in the row and column paths through the rdram interface. 997-t cycle figure 16 figure 17 t cac cas access delay - the interval from rd command to q read data. the equation for t cac is given in the tparm register in figure 40. 98812t cycle figure 5 figure 40 t cwd cas write delay (interval from wr command to d write data. 6 6 6 6 t cycle figure 5 t cc cas-to-cas time of rdram bank - the interval between successive colc commands). 444-t cycle figure 16 figure 17 t pa cke t length of rowa, rowr, colc, colm or colx packet. 4 4 4 4 t cycle figure 3 t rtr interval from colc packet with wr command to colc packet which causes retire, and to colm packet with bytemask. 888-t cycle figure 18 t offp the interval (offset) from colc packet with rda command, or from colc packet with retire command (after wra automatic pre- charge), or from colc packet with prec command, or from colx packet with prex command to the equivalent rowr packet with prer. the equation for t offp is given in the tparm register in figure 40. 4444t cycle figure 15 figure 40 t rdp interval from last colc packet w ith rd command to rowr packet with prer. 444-t cycle figure 16 t rtp interval from last colc packet with automatic retire command to rowr packet with prer. 444-t cycle figure 17 a. or equivalent prec or prex command. see figure 15. b. this is a constraint imposed by the core, and is therefore in units of s rather than t cycle .
direct rdram ? page 16 version 1.41 jan. 2004 k4r761869a absolute maximum ratings note*) component : refer to t j, jc module : refre to t plate, max i dd - supply current profile table 14: absolute maximum ratings symbol parameter min max unit v i,abs voltage applied to any rsl or cmos pin with respect to gnd - 0.3 v dd +0.3 v v dd,abs , v dda,abs voltage on vdd and vdda with respect to gnd - 0.5 v dd +1.0 v t store storage temperature - 50 100 c t min minimum operation temperature 0 note* c table 15: supply current profile i dd value rdram power state and st eady-state transaction rates a min max (1200mhz , -32) max (1066mhz , -32p) max (800mhz, -40) unit i dd,pdn device in pdn, self-refresh enabled and init.lsr=0. - 9000 9000 9000 a i dd,nap device in nap. - 4 4 4 ma i dd,stby device in stby. this is the average for a device in stby with (1) no packets on the channel, and (2) with packets sent to other devices. - 110 110 95 ma i dd,refresh device in stby and refreshing rows at the t ref,max period. - 110 110 95 ma i dd,attn device in attn. this is the average for a device in attn with (1) no packets on the channel, and (2) with packets sent to other devices. - 165 160 135 ma i dd,attn-w device in attn. act command every 8?t cycle , pre command every 8?t cycle , wr command every 4 ? t cycle , and data is 1100..1100 - 980(x18) b 930(x18) 730(x18) ma i dd,attn-r device in attn. act command every 8?t cycle , pre command every 8 ? t cycle , rd command every 4 ? t cycle , and data is 1111..1111 c - 960(x18) 900(x18) 720(x18) ma a. cmos interface consumes power in all power states. b. x18 rdram device data width. c. this does not include the i ol sink current. the rdram device dissipates i ol ? v ol in each output driver when a logic one is driven. table 16: supply current at initialization symbol parameter allowed range of t cycle v dd min max unit i dd,pwrup,d i dd from power -on to setr 1.667ns to 2.5ns v dd,min - 200 a ma i dd,setr,d i dd from setr to clrr 1.667ns to 2.5ns v dd,min - 332 ma a. the supply current will be 150ma when tcycle is in the range 15ns to 1000ns.
direct rdram ? page 17 k4r761869a version 1.41 jan. 2004 capacitance and inductance table 17: rsl pin parasitics symbol parameter and conditions - rsl pins min max unit figure l i rsl effective in put inductance @ t cycle =1.667ns -3.5 nh figure 63 rsl effective in put inductance @ t cycle =1.875ns -3.5 rsl effective in put inductance @ t cycle =2.5ns -4.0 l 12 mutual inductance between any dqa or dqb rsl signals. - 0.2 nh figure 63 mutual inductance between any row or col rsl signals. - 0.6 nh ? l i difference in l i value between any rsl pins of a single device. - 1.8 nh figure 63 c i rsl effective input capacitance a @ t cycle =1.667ns 2.0 2.3 pf figure 63 rsl effective input capacitance a @ t cycle =1.875ns 2.0 2.3 rsl effective input capacitance a @ t cycle =2.5ns 2.0 2.4 c 12 mutual capacitance between an y rsl signals. - 0.1 pf figure 63 ? c i difference in c i value between aver age of {ctm, ctmn, cfm, cfmn} and any rsl pins of a single device. - 0.06 pf figure 63 r i rsl effective in put resistance @ t cycle =1.667ns 410 ? figure 63 rsl effective in put resistance @ t cycle =1.875ns 410 rsl effective in put resistance @ t cycle =2.5ns 415 a. this value is a combination of the device io circuitry and package capacitances table 18: cmos pin parasitics symbol parameter and conditions - cmos pins min max unit figure l i ,cmos cmos effective inpu t inductance - 8.0 nh figure 63 c i ,cmos cmos effective input capacitance (sck,cmd) a 1.7 2.1 pf c i ,cmos,sio cmos effective input capacitance (sio1, sio0) a -7.0pf a. this value is a combination of the device io circuitry and package capacitances.
direct rdram ? page 18 version 1.41 jan. 2004 k4r761869a center-bonded wbga package (92balls) figure 4 shows the form and dimensions of the recom- mended package for the 92balls center-bonded wbga device class. figure 4: center-bonded wbga package table 19 lists the num erical values co rresponding to dimen- sions shown in figure 4. ab cde fgh j 1 2 3 4 5 6 7 d a e1 d e e1 8 e2 top bottom bottom 9 10 klmnprstu bottom table 19 : center-bonded wbga package dimensions symbol parameter min. max . unit e1 ball pitch (x-axis) 0.80 0.80 mm e2 ball pitch (y-axis) 0.80 0.80 mm a package body length 13.3 13.5 mm d package body width 15.0 15.2 mm e package total thickness 0.90 1.00 mm e1 ball height 0.30 0.40 mm d ball diameter 0.40 0.50 mm

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